Dynamic random access memory (DRAM) devices are a well known type of semiconductor memory device. Typically, a DRAM device includes a memory cell block array that includes a plurality of memory cells or “bit cells.” Each of these bit cells can be used to store a single bit of data.
As is well known to those of skill in the art, DRAM devices typically perform a pre-charging operation in which a bit line and a complementary bit line are pre-charged to a predetermined voltage. The bit line delivers a voltage to a capacitor that is part of each bit cell, and the complementary bit line carries a signal that has a logic state which is the inverse of the bit line. During the pre-charge operation, both the bit line and the complementary bit line are pre-charged to a predetermined voltage before a bit cell data read operation or “active” operation is performed.
During a bit cell read operation, charge stored in the capacitor of the bit cell is shared with the bit line, thus producing a small voltage change in the bit line, while the complementary bit line maintains the precharge voltage or has a reference voltage supplied to it by a separate reference circuit. A sense amplifier may then sense the voltage difference between the bit line and the complementary bit line. The sense amplifier amplifies this voltage differential to a larger voltage differential such as, for example, the voltage difference between the supply voltage (VDD) and a ground voltage (VSS) or other reference voltage, and outputs the amplified voltage differential.
The precharge voltage may, for example, be the supply voltage VDD, a half supply voltage VDD/2, or the ground or other reference voltage VSS. When either the supply voltage VDD or the reference voltage VSS is used as the precharge voltage, problems may arise during bit cell data read operations because, depending upon the data stored in the bit cell, the bit line and the complementary bit line may be charged to the same voltage. For instance, when the ground voltage VSS is used as the precharge voltage, if the data in the bit cell is in a first logic state, i.e., “0”, both the bit line and the complementary bit line may maintain the ground voltage VSS, resulting in a failure to change the voltage of the bit line. Likewise, when the supply voltage VDD is used as the precharge voltage, if the data in the bit cell is in a second logic state, i.e., “1”, both the bit line and the complementary bit line may maintain the supply voltage VDD, resulting in a failure to change the voltage of the bit line.
Using the half supply voltage VDD/2 may resolve the aforementioned problems with bit cell data read operations that may occur if the supply voltage VDD or the reference voltage VSS is used as the precharge voltage. In particular, if the half supply voltage VDD/2 is used as the precharge voltage, during bit cell data read operations a predetermined difference between the voltage applied to the bit line and the voltage applied to the complementary bit line will exist when the bit cell data is in either the first or second logic states. However, using the half supply voltage VDD/2 as the precharge voltage may create its own problems, because it requires a mechanism for generating the half supply voltage VDD/2 that is used to precharge the bit lines. Typically, a high-capacity half VDD generator is used to generate the half supply voltage VDD/2, but such a voltage generator may occupy a large area on the chip and increase power consumption due to the need for a large standby current.
During the bit line data read operation, the complementary bit line may have the reference voltage provided by a separate reference circuit. FIG. 1 is a schematic diagram of the peripheral circuit for a reference word line of a conventional semiconductor memory device that provides a reference voltage using a separate reference voltage generator. As shown in FIG. 1, a reference voltage control signal RPRE is activated (i.e., set to logic “1”) prior to the bit cell data read operation, thereby activating a transistor M2 and charging the reference capacitor CL to the half supply voltage VDD/2. During the bit cell data read operation, the reference word line signal RWL is activated in order to activate a transistor M1, thus causing a predetermined difference between a voltage applied to a complementary bit line BLB and a voltage applied to the bit line (which is not depicted in FIG. 1). However, in the technique depicted in FIG. 1, a half supply voltage VDD generator is needed to precharge the reference capacitor CL to the half supply voltage VDD/2. As noted above, the half supply voltage VDD generator may occupy a large area on a chip and causes power consumption due to a large standby current.
FIG. 2 is a schematic diagram of the peripheral circuit for a reference word line of a conventional semiconductor memory device that provides a reference voltage using a half reference capacitor. Referring to FIG. 2, the reference voltage control signal RPRE is activated prior to the bit cell data read operation, thereby activating a transistor M2 so as to precharge a reference capacitor CL/2 to the reference voltage VSS. Typically, the capacitance of the reference capacitor CL/2 is set to be approximately half the capacitance of the capacitor that Stores the bit cell data (not depicted in FIG. 2). During the bit cell data read operation, the reference word line signal RWL is activated in order to activate a transistor M1, thus causing a predetermined difference between the voltage applied to the complementary bit line BLB and the voltage applied to the bit line (which is not depicted in FIG. 2). However, the precharge technique depicted in FIG. 2 typically requires modification of the cell array manufacturing process.